#ifndef __DMA_H__
#define __DMA_H__

#define DMA_CLEAR_FLAG(x) (DMA_DSR_BCR_REG(DMA_BASE_PTR, (x))|=DMA_DSR_BCR_DONE_MASK)
#define DMA_START(x) (DMA_DCR_REG(DMA_BASE_PTR, (x))|=DMA_DCR_START_MASK)
#define DMA_DAR_SET(x, y) (DMA_DAR_REG(DMA_BASE_PTR, (x))=(y))
#define DMA_SAR_SET(x, y) (DMA_SAR_REG(DMA_BASE_PTR, (x))=(y))
#define DMA_BCR_SET(x, y) (DMA_DSR_BCR_REG(DMA_BASE_PTR, (x))|=(y))

#define DMA_ADC_CHN 4

#define DMA_CH0 0
#define DMA_CH1 1
#define DMA_CH2 2
#define DMA_CH3 3

#define DMA_32bit 0x0
#define DMA_8bit 0x1
#define DMA_16bit 0x2

#define DMA_CYCL_MASK 0x4
#define DMA_SINC_MASK 0x2
#define DMA_DINC_MASK 0x1

#define DMAMUX_ADC0 40

#define DMAMUX_CH0 0
#define DMAMUX_CH1 1 
#define DMAMUX_CH2 2 
#define DMAMUX_CH3 3

int dma_memory_init(int8_t ch, uint32_t *sar, uint32_t volatile *dar, uint32_t byte, uint8_t ssize, uint8_t dsize, uint8_t trans_t);
int dma_periph_init(int8_t ch, uint8_t periph, uint32_t volatile *sar, uint32_t *dar, uint32_t byte, uint8_t ssize, uint8_t dsize, uint8_t trans_t);
int dmamux_enable(int8_t ch);
int dma_irq_enable(int8_t ch);
int dma_irq_disable(int8_t ch);
int dma_linkcc(int8_t sch, uint8_t type, int8_t ch1, int8_t ch2);

#endif /* __DMA_H__ */
